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Thanks for the detailed reply. You saying that "They themselves claim that they don’t spend more than €5 per phone on fair trade or environmental stuff" is a complete lie. It's not a number they're claiming, it's a number you've estimated. And lets be clear: what you've done is take $3k in gold credits plus $13k cobalt credits and multiplied that by an arbitrary 8x.

I think you've gone into your analysis with a foregone conclusion. There simply isn't enough information to say anything about the cost overheat of being "fair".

You’ll likely find almost identical amounts of recycled materials in any other phone, because it makes economical sense. It’s just cheaper.

And yet the FP4 was significantly less recycled. Plastic is certainly not cheaper to recycle; that's a lie the plastic industry's been pushing for a while.

they stop selling parts quickly

That's weird. If they stopped making parts how did I get a replacement battery for my fairphone 3?

Have a look at their impact report. They themselves claim that they don’t spend more than €5 per phone on fair trade or environmental stuff.

I've looked through their report and I can't find this info. The only thing I've found is a ~€2 bonus per phone to their factory workers, which is only a small fraction of a phones supply chain. Can you provide a more detailed reference supporting your claim?

Wirelessly.

FairPhone doesn't do wireless charging.

A big problem they have is that they have to rely on Qualcomm for security updates, and the flagship chips simply don't get 8+ years of support. Fairphone uses Qualcomms IOT chips, which come with much longer support.

Sure, but it's not more valuable than $30 + regular price increases for 60+ years. That's what a lifetime membership is.

Lets flip that around: For my own finances $300 is a lot more valuable than $30 for 10 years. So if I'm to expect that the company will go out of business in 10 years or so, I would have been better off paying for the subscription.

Lets also not forget that companies don't take that $300 and responsibly invest it. It gets reinvested in a risky bid to grow the company and get enough people to subscribe in order to pay for your service going forward.

Lifetime services/updates are always a scam. The economics of this are really simple: Nebula is $30 per year or $300 lifetime. That lifetime membership covers only 10 years of subscription. So what's the plan after that? There's only really three outcomes:

• They stop providing you service
• They go bankrupt trying to provide you service
• They grow and stay big enough to be able to subsidize your service for your lifetime. I can't overstate how unlikely this is.

Buying a lifetime membership you're gambling that Nebula will grow big enough that other people's subscription will pay for your service. Your membership is a liability for them.

It's also bad from the other end. Lots of small software devs will sell lifetime updates but eventually need to abandon their products because they simply run out of money.

A service continually costs money to provide. You can't pay for that with a single payment. Lifetime services are simply incompatible with running a business long term. It's a bad idea and someone is always getting screwed.

Support for 2015 macs ended 7 months ago. Forget 10 years ago, my 2015 mac doesn't run like it used to in Big Sur.

I'm more familiar with RISC-V than I am with ARM though it's my understanding they're quite similar.

• ARM/RISC-V are load-store architectures, meaning they divide instructions between loading/storing and doing computation. x86 on the other hand is a register-memory architecture, having instructions that do both computation as well as loading/storing.

• ARM/RISC-V also have weaker guarantees as to memory ordering allowing for less synchronization between cores, however RISC-V has an extension to enforce the same guarantees as x86 and Apple's M-series CPU have a similar extension for ARM. If you want to emulate x86 applications on ARM/RISC-V these kinds of extensions are essential for performance.

• ARM/RISC-V instructions are variable width but only in a limited sense. They have "compressed instructions" - 2 bytes instead of 4 - to increase instruction density in order to compete with x86's true variable width instructions. They're fairly close in instruction density, though compressed instructions are annoying for compilers to handle due to instruction alignment. 4 byte instructions must be aligned to 4 bytes, so if you have 3 instructions A, B and C but only B has a compressed version then you can't actually use it because there must be 4 bytes between instructions A and C.

• ARM/RISC-V also makes backwards compatibility entirely optional, Apple's M-series don't implement 32-bit mode for instance, whereas x86-64 still has "real mode" for running 16 bit operating systems.

There's also a number of other differences, like the number of registers, page table formats, operating modes, etc, but those are the more fundamental ones I can think of.

Up until your post I had thought it exactly was the size of the instruction set with x86 having lots of very specific multi-step-in-a-single instruction as well as crufty instruction for backwards compatibility (like MPSADBW).

The MPSADBW thing likely comes from the hackaday article on why "x86 needs to die". The kinda funny thing about that is MPSADBW is actually a really important instruction for (apparently) video decoding; ARM even has a similar instruction called SABD.

x86 does have a large number of instructions (even more so if you want to count the variants of each), but ARM does not have a small number of instructions and a lot of that instruction complexity stops at the decoder. There's a whole lot more to a CPU than the decoder.

compressed instruction set /= variable-width [...]

Oh for sure, but before the days of super-scalars I don't think the people pushing RISC would have agreed with you. Non-fixed instruction width is prototypically CISC.

For simpler cores it very much does matter, and “simpler core” here can also could mean barely superscalar, but with insane vector width, like one of 1024 GPU cores consisting mostly of APUs, no fancy branch prediction silicon, supporting enough hardware threads to hide latency and keep those APUs saturated. (Yes the RISC-V vector extension has opcodes for gather/scatter in case you’re wondering).

If you can simplify the instruction decoding that's always a benefit - moreso the more cores you have.

Then, last but not least: RISC-V absolutely deserves the name it has because the whole thing started out at Berkeley.

You'll get no disagreement from me on that. Maybe you misunderstood what I meant by "CISC-V would be just as exciting"? I meant that if there was a popular, well designed, open source CISC architecture that was looking to be the eventual future of computing instead of RISC-V then that would be just as exciting as RISC-V is now.

The original debate from the 80s that defined what RISC and CISC mean has already been settled and neither of those categories really apply anymore. Today all high performance CPUs are superscalar, use microcode, reorder instructions, have variable width instructions, vector instructions, etc. These are exactly the bits of complexity RISC was supposed to avoid in order to achieve higher clock speeds and therefore better performance. The microcode used in modern CPUs is very RISC like, and the instruction sets of ARM64/RISC-V and their extensions would have likely been called CISC in the 80s. All that to say the whole RISC vs CISC thing doesn't really apply anymore and neither does it explain any differences between x86 and ARM. There are differences and they do matter, but by an large it's not due to RISC vs CISC.

As for an example: if we compare the M1 and the 7840u (similar CPUs on a similar process node, one arm64 the other AMD64), the 7840u beats the M1 in performance per watt and outright performance. See https://www.cpu-monkey.com/en/compare_cpu-amd_ryzen_7_7840u-vs-apple_m1. Though the M1 has substantially better battery life than any 7840u laptop, which very clearly has nothing to do with performance per watt but rather design elements adjacent to the CPU.

In conclusion the major benefit of ARM and RISC-V really has very little to do with the ISA itself, but their more open nature allows manufacturers to build products that AMD and Intel can't or don't. CISC-V would be just as exciting.

CRTs (apart from some exceptions) did not have a display buffer. The analog display signal is used to directly control the output of each electron gun in the CRT, without any digital processing happening in-between. The computer on the other end however does have display buffers, just like they do now; however eliminating extra buffers (like those used by modern monitors) does reduce latency.