Technology

59534 readers

3195 users here now

This is a most excellent place for technology news and articles.

Our Rules

Follow the lemmy.world rules.
Only tech related content.
Be excellent to each another!
Mod approved content bots can post up to 10 articles per day.
Threads asking for personal tech support may be deleted.
Politics threads may be removed.
No memes allowed as posts, OK to post as comments.
Only approved bots from the list below, to ask if your bot can be added please contact us.
Check for duplicates before posting, duplicates may be removed

Approved Bots

founded 1 year ago

MODERATORS

237

DC-ROMA Laptop II packs an octa-core RISC-V processor, 16GB of RAM and Ubuntu Linux - Liliputing (liliputing.com)

submitted 5 months ago by schizoidman@lemmy.ml to c/technology@lemmy.world

19 comments fedilink hide all child comments

you are viewing a single comment's thread
view the rest of the comments

[–] barsoap@lemm.ee 1 points 5 months ago* (last edited 5 months ago) (1 children)

You can keep the array processors fed with low IPC and frequency by having absolutely massive vector lengths, the engineering for that kind of processor isn't in the pipeline, branch prediction etc. it's in the APUs and how to stream data into them. Much more like GPUs, in fact RISC-V has instructions for gather/scatter.

[–] wewbull@feddit.uk 1 points 5 months ago

Disagree. You quite often have a fair degree of scaler code in between portions which are embarrassingly parallel. If you don't have a decent scaler core you are destined to be become bottlenecked on them. It's not that different to a CPU / GPU pairing. If one is under powered, it determines the speed of the overall system.

If you look at what a company like Tenstorrent is doing, they are designing high performance Risc-V cores as a side aspect of their main goal of doing array processors. The reason is because they couldn't find scaler cores on the market with enough performance to not bottleneck the system.