this post was submitted on 07 Dec 2024
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"Ousted" Intel CEO Steps In To Defend The Firm's 18A Process, Says Yield Rate % Isn't The Right Metric To Measure Semiconductor Progress (wccftech.com)
submitted 1 week ago by floofloof@lemmy.ca to c/technology@lemmy.world
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[–] wewbull@feddit.uk 13 points 1 week ago

All depends on the maturity of the process. 10% for a new design on a bleeding edge process is possibly viable. You'll then tweak the design and process to get the yield up.